One or more aspects relate, in general, to debugging circuits, and in particular, to debugging scan latch circuits.
Failures in chains of conventional scan-only latches are very difficult to debug. This is because data is loaded into these chains through a serial scanning process. If the chain is broken, predictable values cannot be input into the latches which are downstream from the break. Thus, when scanning out and observing the output of the chain, it is not known when the first “wrong” value appears at the output (i.e., indicating the failing latch bit). That is, some, or all, of the latch bits downstream from the failing latch are initialized to the value set by the failing latch when scanning the chain. Therefore, the output just shows a steady stream of values set by the value of the latch bit stuck at a particular value making it difficult to determine which latch in the chain is the failed or broken latch.
Various solutions to the problem have been attempted, including using logic gates, such as exclusive OR gates, or other electronic devices, such as multiplexors, to debug the chain of latches. However, these solutions tend to be costly.